1. Field of the Invention
The present invention relates to a processing apparatus including a master processing module and a plurality of slave processing modules connected to the master processing module, and relates also to a processing module included in the processing apparatus. In particular, the present invention relates to a processing apparatus and a processing module in which the overall cost of the cache memories of the processing apparatus is reduced and the overall processing speed of the processing apparatus is improved.
2. Description of Related Art
In recent years, the mobile telephone service has expanded, and wireless networks where enormous amounts of data such as sounds and images are transmitted and received have been spreading. Therefore, a base transceiver station has been required that is capable of coping with the upsurge in traffic volume resulting from the expansion of the mobile telephone service and the spread of wireless networks. With this being the situation, a processing apparatus formed of a multiprocessor using one master processing module having a shared memory and a plurality of slave processing modules under the control of the master processing module is used as a base transceiver station.
FIG. 1 is a block diagram conceptually showing the structure of a conventional processing apparatus. In FIG. 1, reference numeral 1000 represents the processing apparatus used as a base transceiver station. The processing apparatus 1000 includes one master processing module 1100 and a plurality of slave processing modules 1200. The master processing module 1100 and the slave processing modules 1200 are interconnected by connection cables constituting a bus topology.
The master processing module 1100 includes a CPU 1110 and a shared memory 1120. Each of the slave processing modules 1200 includes a CPU 1210, a cache memory 1220, and a management table 1230 indicating the contents recorded in the cache memory 1220. In the cache memory 1220 included in each slave processing module 1200, part of the data recorded in the shared memory 1120 of the master processing module 1100 is recorded.
When it is necessary for a slave processing module 1200 to access the data recorded in the shared memory 1120, the slave processing module 1200 determines whether the necessary data is recorded in its own cache memory 1220 or not by referring to its own management table 1230. When the necessary data is recorded in its own cache memory 1220, the slave processing module 1200 accesses the data recorded in its own cache memory 1220. When the necessary data is not recorded in its own cache memory 1220, the slave processing module 1200 acquires the communication right (bus use right), and then, accesses the master processing module 1100, more specifically, accesses the data recorded in the shared memory 1120 included in the master processing module 1100. The result of the access is reflected in the cache memories 1220 of all the slave processing modules 1200.
Such a system is disclosed, for example, in Japanese Patent Application Laid-Open No. H07-225737.